Associative processor T161

T161 is a simple 16-bit general processor with associative capabilities. Besides the normal instructions for data movement, arithmetic and logic operations, as well as changing the control flow, the processor is partially capable of performing SIMD parallel instructions. It contains an integrated associative memory (CAM) that operates at the speed of registers. Parallel instructions can be executed on the associative memory or parts of it, thus dramatically speeding up the computation. Some algorithms can be implemented to take advantage of the associative capabilities and thus run up to 8x faster.

The idea of T161 was to create a processor that is simpler than the popular STARAN and PEPE, but that also provides associative computation. The processor was developed within a practice course in the Computer Architecture Group at University of Technology Darmstadt, Germany. I would like to thank Prof. Dr. Rolf Hoffmann for supervising the development.

Processor capabilities

The T161 is built upon a Harvard architecture and has a separate program and data memories. Internally it works with 16-bit signed data. It supports the following types of instructions:

• Data movement
• Arithmetic and logic instructions
• Control flow instructions ((un)conditional branches)
• Vector operations (parallel instructions)

Speed

The processor works with an input frequency of up to 14 MHz. It can though be overclocked to over 50 MHz, but slight changes are required.

Memory

The T161 uses a Harvard architecture and has a separate program and data memory. Both of them are synchronous and word-addressable. The program memory uses a word size of 32-bit and the data memory - a word size of 16-bit. The memories are supposed to be clocked at the same frequency as the processor, but this is not obligatory. The processor is able to work with memories of different speeds. The maximum capacity of the program memory is 256 KB and of the data memory - 128 KB.

Software

The processor suite contains also an assembler that is able to compile T161 assembly files to binaries, ready to be copied to a memory chip. A tool for converting to .mif (memory initialization file) is also included, so it can easily be tested on Altera FPGAs. A documentation is also available.

Status

The processor is completely implemented and is ready to be synthesized to FPGA or ASIC. It has been tested on an Altera Cyclone III FPGA. For more information, contact me.